Nanomagnetic Self-Organizing Logic Gates

The end of Moore’s law for CMOS technology has prompted the search for low-power computing alternatives, resulting in promising approaches such as nanomagnetic logic. However, nanomagnetic logic is unable to solve a class of interesting problems efficiently, as it only allows for forward computing, due to the need for clocking and/or thermal annealing. Here, we introduce nanomagnetic self-organizing logic gates that can dynamically satisfy their logical proposition, irrespective of whether the signal is applied to the traditional input or output terminals, thus allowing for reversible computing. We present a design of a self-organizing nand gate, the logically correct states of which are occupied equally in thermodynamical equilibrium, and illustrate its capabilities by implementing reversible Boolean circuitry to solve a two-bit factorization problem via numerical modeling. Our approach offers an alternative path to explore memcomputing, an unconventional computing paradigm the usefulness of which has already been demonstrated by solving a variety of hard combinatorial optimization problems.

Figure 1

The effect of balancedness on a logic circuit. (a) The Boltzmann probability distribution for a unbalanced and a balanced nand gate. The relative probability $P_{\mathrm{rel}}$ is obtained by dividing the probabilities of all of the possible states by the probability of the most likely logical state. The inputs (marked in yellow) and the output (marked in green) are “free,” i.e., they can take the logical values 0 and 1. (b) The Boltzmann probability distribution for three nand gates in series, with free inputs and a free output. The terminals that are connected always share the same logical value. The horizontal red line indicates the probability of the most likely logically incorrect state, while the horizontal blue line indicates the probability of the least likely logical state. If the circuit consists of unbalanced gates (upper panel), some logically correct states are indistinguishable from the logically incorrect states. In contrast, the same circuit built up out of balanced gates does not suffer from this problem (lower panel).

Figure 2

The balancedness of the so-nand gate. (a) A balanced so-nand gate consisting of four nanomagnetic islands, schematically represented by circles. The input islands (marked “A” and “B”) are shown in yellow and the output (marked “O”) in green. The black circle represents a bias island with fixed magnetization $m_z=-1$ and with a magnetic moment that is 22.6 times as large as that of the input and output islands. $R=11.34$ nm. (b) A balanced so-nand gate on a regular triangular grid, with multiple fixed-bias islands (black, $m_z=-1$; gray, $m_z=+1$). The magnetic moment of the bias islands is the same as that of the input and output islands, (c) Boltzmann probabilities based on the two-state model. Although the total probability of logically correct states decreases with increasing temperature, their individual probabilities remain matched as the thermal energy is varied. (d) The island macrospin dynamics are simulated at 300 K, as indicated by the vertical dashed line in panel (c). The likelihood of each logical state is shown for a varying relative magnetic moment of the fixed-bias island(s). To recover the balancedness, the bias island(s) should have a magnetic moment of only 90% (as indicated by the arrow) relative to the value obtained with the two-state model.

Figure 3

The probabilities of the logical states, obtained with a dynamical macrospin approach using different relative bias strengths for varying (a) damping, (b) temperature, and (c) anisotropy constant. The highlighted region corresponds to the simulation parameters used throughout this work.

Figure 4

A schematic representation of the dynamic-error-suppression (DES) scheme. The logical correctness of the gate is periodically checked, i.e., after a time ${\tau }_{\mathrm{DES}}$. If the gate is found to be in a logically incorrect state, an additional biasing field is applied on each input and output island for a duration of ${\tau }_{\mathrm{on}}$. (a) ${\tau }_{\mathrm{DES}}=4{\tau }_{\mathrm{on}}$. (b) ${\tau }_{\mathrm{DES}}$ = ${\tau }_{\mathrm{on}}$.

Figure 5

The performance of the so-nand gate and the so-xnor gate with dynamic error suppression (DES). (a) The state probability distributions of a so-nand gate for different DES check times, ${\tau }_{\mathrm{DES}}$. The relative probability $P_{\mathrm{rel}}$ is obtained by dividing the probabilities of all of the possible states by the probability of the most likely logical state. (b) The so-nor gate is realized with the same geometry as the balanced so-nand gate, the only difference being the reversed magnetization of the fixed-bias island. (c) A schematic representation of a so-xnor gate. (d) The state probability distributions of a so-xnor gate for different ${\tau }_{\mathrm{DES}}$. The symbol “?” means that input islands A or input islands B are not logically consistent. All logically inconsistent states are aggregated into the $X$ state ($X$ stands for 0 or 1).

Figure 6

SO gates with a fixed output. (a) The balancedness of a so-nand gate with output 1 is recovered at a relative bias of 1.04, corresponding to the point where the probabilities of all logically correct states are equal, as indicated by the arrow. The two-state model corresponds to a relative bias of 1. (b) The state probability distributions of a so-nand gate with fixed output. The relative probability $P_{\mathrm{rel}}$ is obtained by dividing the probabilities of all of the possible states by the probability of the most likely logical state. (c) The state probability distributions of a so-xnor gate with a fixed output.

Figure 7

The operation of a self-organizing two-bit multiplier. A schematic representation of a self-organizing two-bit multiplier and the state probability distributions for a fixed output, showing that for any fixed output, we retrieve the correct factorization(s) with a high probability. The relative probability $P_{\mathrm{rel}}$ is obtained by dividing the probabilities of all of the possible states by the probability of the most likely logical state. All states for which one of the inputs is logically inconsistent are aggregated into the “$?,?$” state. The rate at which the DES scheme is applied, ${\tau }_{\mathrm{DES}}$, is set to $4{\tau }_{\mathrm{on}}$.