Vertical Transistors with Conductive-Network Electrodes: A Physical Image and What It Tells

Vertical transistors with conductive-network electrodes composed of carbon- or metal-based nanowires or meshes are attractive because of their high current density, low operational voltage, and high degree of integration. However, the devices lack concise physical images to understand the operations and explicit design rules to achieve the necessary performance, such as sharp subthreshold swing and a large on:off ratio. Here, we develop a device theory with concise physical images, which are generally applicable for devices with organic or inorganic semiconductors. The simplified solution of Poisson’s equation reveals that the electrostatic potential at the semiconductor-dielectric interface is controlled by both the gate and drain field, behaving like a plucked string. The spacing between electrodes and the capacitance ratio between semiconductors and dielectrics are critical for achieving strong gate tunability of the interfacial potential, and such gate tunability can be maximized to achieve a sharp turn-on property toward the Boltzmann limit in the subthreshold regime. Above the threshold, the conduction channels in devices with Schottky contacts can change from the “L type” to “I type”, or vice versa, during scanning and the current-voltage relations can be well described by modifying classical transistor equations. The derived theories and equations agree well with the numerically simulated devices and reported experiments, revealing the physical images and providing explicit rules for designing, fabricating, and characterizing such transistors.

Figure 1

Device concepts and channel positions. (a), (b) Three-dimensional simulated devices with contours of current density. Main device parameters are as follows: width of cuboid source electrodes is d_S (20 nm), spacing between electrodes is d_gap (200 nm), semiconductor layer thickness is t_SC (320 nm), insulator layer thickness is t_ox (50 nm), and energy offset between the work function of the electrodes and electron affinity of the semiconductor is qφ_b. Device in (a) has Ohmic contacts (qφ_b = 0.0 eV, V_G = 1 V, and V_D = 10 V), whereas that in (b) has Schottky contacts (qφ_b= 0.4 eV, V_G = 20 V, and V_D = 1 V). Current density unit is A cm⁻². (c)–(e) Schematic representations of the current distribution and resistances, which depend on the contact properties and operational modes.

Figure 2

Potential distribution. (a)−(c) Interfacial potential ${\varphi }_s$ near single-source electrode: (a) scheme showing ${\varphi }_s(x)$ at zero V_G and V_D (black), positive V_G or V_D (red), and negative V_G or V_D (blue); (b) ${\varphi }_s(x)$ as a function of x for various V_G [dots are TCAD-simulated, and the curves are fitted by Eq. (4), the same below]; (c) ${\varphi }_s$ as a function of V_G for various x. ${\varphi }_{s0}$ is the reference point. (d)–(f) ${\varphi }_s$ between neighboring electrodes: (d) scheme showing regulating ${\varphi }_s$ by V_G; the capacity for regulation (or sensitivity) decreases when d_gap decreases. (e),(f) ${\varphi }_s$ in a device with d_gap= 200 or 50 nm [dots are TCAD-simulated and curves are fitting by Eq. (6a)]. (g)–(i) 2D distribution of potential $\varphi$: (g) scheme showing potential distribution in the vertical direction; (h),(i) TCAD-simulated 2D distribution of potential of the semiconductor layer in a device with d_gap= 200 or 50 nm (5 source electrodes). Dashed lines label the position with a distance of d_gap from the top of the source. Parameters of the TCAD-simulated device are qφ_b = 0.4 eV, t_ox= 10 nm, and t_SC= 320 nm.

Figure 3

Band bending, carrier density, and channel formation. TCAD-simulated results along the two arrows in Fig. 2, i.e., at the semiconductor-dielectric interface between two source electrodes (x direction) and from one source to the drain electrode (y direction). For V_G tuning, the energy levels of E_c and E_Fn are shown in (a) and (b) with solid and dashed curves, respectively. Carrier density n is shown in (e),(f), and the vertical component of current density J_y is shown in (i), (j). For V_D tuning, the energy levels, n, and J_y are shown in (c), (d), (g), (h), (k), and (l). (m)–(p) 2D log₁₀-scaled current distribution in devices (3 sources) during transfer scanning (m),(n) or output scanning (o),(p). Parameters of the TCAD-simulated device are qφ_b = 0.4 eV, t_ox= 10 nm, t_SC= 320 nm, and d_gap= 200 nm.

Figure 4

Subthreshold transfer characteristics. (a) Differential change of ${\varphi }_s(x)$ to V_G. Devices have varied d_gap values (d_gap= 10–200 and ∞, t_ox= 10 nm). Dots are TCAD-simulated data and curves are calculated from Eq. (7a). (b),(c) Transfer curves for devices with d_gap= 200 nm and an oxide thickness, t_ox, of 10 (b) or 100 nm (c). Only the source current, I_S, from the middle of five neighboring electrodes is shown, the same below. In (b), data of conventional TFT with the same materials (W/L = 0.5 and the semiconductor is 20 nm thick) are shown as a reference (gray dashed curve). (d) Extracted S_S values (V_D= 0.1 V) as a function of t_ox for devices with d_gap= 50 nm (red) or d_gap= 200 nm (black). (e),(f) Transfer curves of devices with d_gap= 50 nm and t_ox= 10 (e) or 100 nm (f). Parameters of the TCAD-simulated device are qφ_b = 0.4 eV, t_ox= 10 or 100 nm, t_SC= 320 nm, and d_gap= 20–200 nm.

Figure 5

Above-threshold transfer characteristics. (a)−(c) Device operated with varied V_D: (a) source current I_S from a 2D TCAD-simulated device (dots) and from fitting with Eq. (12) (curves) for various V_D values. (b) Corresponding transconductance g_m. (c) Fitting parameter equivalent channel length λ (top) and extracted parameter contact resistance R_side,C (normalized with the channel width W, bottom). (d)−(f) Devices with varied d_gap operated at V_D = 0.1 V: (d) source current I_S with varied d_gap values, from a 2D TCAD-simulated device (dots) and from fitting with Eq. (12) (curves). (e) Corresponding transconductance g_m. (f) Corresponding λ and R_side,C. Parameters of the 2D TCAD-simulated device are qφ_b = 0.4 eV, t_ox= 10 nm, t_SC= 320 nm, and d_gap= 20–200 nm.

Figure 6

Output characteristics. (a) Output characteristics for various V_G values from the TCAD-simulated devices (dots) and fitting (curves). (b) Extracted differential output resistance R_dif, all of which gradually approach constant R_top. (c) Extracted R_top (normalized by W) from the output characteristics as a function of the injection barrier qφ_b, with the dashed line showing $R_{\mathrm{top}}\propto \mathrm{exp(}q{\phi }_b/kT)$. Dots from various V_G values overlap. (d) Output characteristics for devices with various film thicknesses of semiconductor t_SC from 40 to 320 nm (V_G = 2 V). (e) Extracted R_dif. (f) Extracted R_top (normalized by W) from devices with various t_SC values (red dots). Red line represents values calculated from Eq. (15). Parameters of the TCAD-simulated device are qφ_b = 0.4 eV, t_ox= 10 nm, and d_gap= 200 nm. In (f), data of R_top for devices with d_gap= 50 nm are also shown (blue dots and line).

Figure 7

Current density and on:off ratio. Extracted values of J_on and current ratio between V_G = 5 V and −5 V for devices (V_D = 0.1 V) with various (a) qφ_b, (b) t_ox, (c) t_SC, or (d) d_gap values. Parameters of the TCAD-simulated device are based on qφ_b = 0.4 eV, t_ox= 10 nm, t_SC= 320 nm, and d_gap= 200 nm, and one parameter at a time is changed to investigate the impact.