Factors affecting the output pulse flatness of the linear transformer driver cavity systems with 5th harmonics

We describe the study we have undertaken to evaluate the effect of component tolerances in obtaining a voltage output flat top for a linear transformer driver (LTD) cavity containing 3rd and 5th harmonic bricks [A. A. Kim et al., in Proc. IEEE Pulsed Power and Plasma Science PPPS2013 (San Francisco, California, USA, 2013), pp. 1354–1356.] and for 30 cavity voltage adder. Our goal was to define the necessary component value precision in order to obtain a voltage output flat top with no more than $\pm 0.5\%$ amplitude variation.

Figure 1

Top view of the LTD cavity with 5th harmonics and total number of bricks $s+m+f=20$. The dimensions here and in Fig. 2 are given in millimeters.

Figure 2

Side view of the LTD cavity with 5th harmonics and total number of the bricks $s+m+f=20$.

Figure 3

The OrCAD models of the standard brick: on the left as presented in [1], and on the right as utilized in the present paper. The models of the 3rd and 5th harmonic bricks were modified in the same way.

Figure 4

The OrCAD model of the ST_S block.

Figure 5

Definition of the maximal $U_{\max }$ and minimal $U_{\min }$ amplitude of the voltage pulse across the resistive load $R$ in Eq. (3.2).

Figure 6

Output power and voltage of the output pulse of the LTD cavity in $11\mathrm{S}+7\mathrm{M}+2\mathrm{F}$ configuration depending on the resistance of the cavity load $R$.

Figure 7

The OrCAD model of the module consisting of 30 series LTD cavities with 5th harmonics terminated with a load of 23.7 Ohm.

Figure 8

With green and red the regions are shown where the top of the pulse at the output of the LTD module has larger variation (red) or smaller (green) than $\pm 0.5\%$ for ${\sigma }_{1C}/\overline{C}=0$. On the curve separating these two regions, the top of the output pulse is $\pm 0.5\%$ flat. Red points on the green section of this graph indicate how the red region would increase (and the green decrease) if the tolerance of the capacitor capacitance ${\sigma }_{1C}/\overline{C}=3.33\%$ is included in the simulations.

Figure 9

The left graph shows the output pulses across the 23.7 Ohm load of the module consisting of 30 LTD cavities connected in series with 5th harmonics in $11\mathrm{S}+7\mathrm{M}+2\mathrm{F}$ configuration, which are simulated with ${\sigma }_{1T}=0.5\mathrm{ns}$, ${\sigma }_{1L}/\overline{L}=1.67\%$, ${\sigma }_{1C}/\overline{C}=0$. The right graph shows the tops of 80 pulses in more detail.