Fault-tolerance thresholds for the surface code with fabrication errors

The construction of topological error correction codes requires the ability to fabricate a lattice of physical qubits embedded on a manifold with a nontrivial topology such that the quantum information is encoded in the global degrees of freedom (i.e., the topology) of the manifold. However, the manufacturing of large-scale topological devices will undoubtedly suffer from fabrication errors—permanent faulty components such as missing physical qubits or failed entangling gates—introducing permanent defects into the topology of the lattice and hence significantly reducing the distance of the code and the quality of the encoded logical qubits. In this work we investigate how fabrication errors affect the performance of topological codes, using the surface code as the test bed. A known approach to mitigate defective lattices involves the use of primitive swap gates in a long sequence of syndrome extraction circuits. Instead, we show that in the presence of fabrication errors the syndrome can be determined using the supercheck operator approach and the outcome of the defective gauge stabilizer generators without any additional computational overhead or use of swap gates. We report numerical fault-tolerance thresholds in the presence of both qubit fabrication and gate fabrication errors using a circuit-based noise model and the minimum-weight perfect-matching decoder. Our numerical analysis is most applicable to two-dimensional chip-based technologies, but the techniques presented here can be readily extended to other topological architectures. We find that in the presence of $8\%$ qubit fabrication errors, the surface code can still tolerate a computational error rate of up to $0.1\%$.

Figure 1

(a) The construction of topological codes (depicted here using the toy example of the toric code) relies on the fabrication of a perfect topology in order for the encoded logical state to be globally protected. (b) Fabrication errors have the drastic effect of damaging the topology and shortening the distance of the code.

Figure 2

An example of a primal lattice of a distance-5 surface code. Each star $s$ and plaquette $p$ of the lattice is associated with a four-body $X$-type ($A_s$) and $Z$-type ($B_p$) stabilizer generator, respectively. The logical operators $X_L$ and $Z_L$ correspond to anticommuting strings that span the lattice, but each commutes with all the stabilizer generators. The left and right edges are the rough edges, and the top and bottom edges are the smooth edges.

Figure 3

Syndrome extraction circuits for $X$-type (left) and $Z$-type (right) stabilizer generators. Each syndrome extraction circuit involves six temporal steps: preparation of the syndrome qubit, four controlled-not (cnot) gates, and syndrome qubit measurement. The data qubits are idle during the preparation and measurement steps. The cnot gates are always applied in a specific order, in this case north ($n$), west ($w$), east ($e$), then south ($s$) (forming a zigzag shape), in order to ensure all stabilizer generators commute when measured.

Figure 4

When a data qubit is disabled or faulty (shown in red with a dashed border), the associated links are disabled (a), resulting in four adjacent damaged check operators. The product of two stabilizer generators is used to form a supercheck operator, effectively removing this qubit from the code. This process occurs in both the primal (b) and dual (c) lattices; the cnot gates shown in this figure are those used when measuring the supercheck operators as products of gauge operators.

Figure 5

Mapping link fabrication errors to disabled data qubits; faulty and disabled components are shown in red with a dashed border. When a link fabrication error occurs (left), the data qubit associated with the link is disabled (middle) and superstars and superplaquettes are formed on the primal and dual lattices, respectively (right).

Figure 6

Mapping syndrome fabrication errors to disabled data qubits; faulty and disabled components are shown in red with a dashed border. When a syndrome qubit fabrication error occurs, all the data qubits involved in the associated stabilizer generator are disabled (a). Large superstars (b) and superplaquettes (c) are formed around these disabled data qubits.

Figure 7

Percolation rates for link fabrication errors only. The crossing point gives a threshold of just under 16%.

Figure 8

Percolation rates for qubit fabrication errors only. The crossing point gives a threshold of around 14.5%.

Figure 9

Average effective code distance for link fabrication errors only.

Figure 10

Average effective code distance for qubit fabrication errors only.

Figure 11

Effective order of gauge operator measurement. If the normal z-shaped measurement pattern is used, the effective order in which the gauge operators are measured is $c$, $\gamma$ & $\beta$, $a$ & $b$, $\alpha$. The anticommutation randomizes the supercheck operator products, so $X$- and $Z$-type gauge operators are instead measured in alternating rounds to ensure the supercheck operator outcome is deterministic.

Figure 12

Dealing with fabrication errors at the edge of the lattice; faulty and disabled components are shown in red with a dashed border. When data qubits at the edge of the lattice are disabled (left, middle), the product of gauge operators is not in the stabilizer, so such stabilizer generators must be disabled rather than forming supercheck operators (right).

Figure 13

Pauli error thresholds for link, $p_{\mathrm{link}}$, and qubit, $p_{\mathrm{qubit}}$, fabrication errors. An exponential is fit applied to each data set: $0.71e^{-20p_{\mathrm{link}}}$ for link fabrication errors and $0.70e^{-22p_{\mathrm{qubit}}}$ for qubit fabrication errors. Individual thresholds plots are available in the Supplemental Material [37].

Figure 14

Logical error rates for codes with fabrication errors with intended distance $L=13$ and actual distance $L^{\prime }=9$ compared to native distance 9 codes with no fabrication errors. The native codes have lower logical error rates.

Figure 15

Rate at which highest-weight supercheck operators occur for link fabrication error rate $p_{\mathrm{link}}=10\%$. The weight of the highest-weight supercheck operator appears to increase logarithmically with code distance, as expected [38].