Error rates and resource overheads of encoded three-qubit gates

A non-Clifford gate is required for universal quantum computation, and, typically, this is the most error-prone and resource-intensive logical operation on an error-correcting code. Small, single-qubit rotations are popular choices for this non-Clifford gate, but certain three-qubit gates, such as Toffoli or controlled-controlled-$Z$ (ccz), are equivalent options that are also more suited for implementing some quantum algorithms, for instance, those with coherent classical subroutines. Here, we calculate error rates and resource overheads for implementing logical ccz with pieceable fault tolerance, a nontransversal method for implementing logical gates. We provide a comparison with a nonlocal magic-state scheme on a concatenated code and a local magic-state scheme on the surface code. We find the pieceable fault-tolerance scheme particularly advantaged over magic states on concatenated codes and in certain regimes over magic states on the surface code. Our results suggest that pieceable fault tolerance is a promising candidate for fault tolerance in a near-future quantum computer.

Figure 1

Logical error rates of 3-qubit gate on (a, b) pieceable 7-qubit code (green, dot-dashed), pieceable $3\times 3$ Bacon-Shor code (blue, dashed), (c, d) pieceable 5-qubit code (green, dot-dashed), pieceable $3\times 9$ Bacon-Shor code (blue, dashed), and magic-state injection on 7-qubit code (orange, solid) with (a, c) $p_1=p_2=p_3=p$ and (b, d) $10p_1=p_2=0.1p_3=p$, where $p_i$ refers to the physical error rate of an $i$-qubit gate. Initialization of single-qubit states $\left|0\right.〉$, $\left|+\right.〉$ also fails with probability $p_1$. Dotted line is the “break-even” line where the logical error rate coincides with the physical error rate.

Figure 2

Logical error rates for 3-qubit gate on the surface codes and (a) pieceable $3\times 3$ Bacon-Shor code and (b) pieceable 7-qubit code in terms of code distance. Shown rates for pieceable codes are upper bounds obtained by concatenating the upper bounding function from Eq. (7). Black dashed curves are only a guide to the eye.

Figure 3

Circuit volume for logical 3-qubit gate on pieceable 7-qubit code (circles), pieceable $3\times 3$ Bacon-Shor code (squares), and magic-state scheme on 7-qubit code (diamonds) in terms of code distance. The dots correspond to every concatenation level in the range. Although it may be hard to see the data for the pieceable 7-qubit code because they are close to the data for the magic-state scheme, the pieceable 7-qubit has slightly lower volume than the magic-state scheme for every distance shown.

Figure 4

The region where pieceable $3\times 3$ Bacon-Shor code (orange and purple) and pieceable 7-qubit code (purple) use less volume than surface codes to implement 3-qubit gate to achieve fixed target logical error rate $p_T$ with fixed physical error rate $p$. Dashed lines labeled by ${\mathbf{ST}}_{\mathbf{j}}$ are upper bounds on the logical error rate at the $j\text{th}$ concatenation level of the pieceable 7-qubit code (Steane code). The dotted line labeled by $\mathbf{SC}\left(\mathbf{7}\right)$ is the logical error rate for the surface code with distance 7. The dot-dashed line labeled by ${\mathbf{BS}}_{\mathbf{3}}$ is an upper bound of logical error rate at the third concatenation level of the $3\times 3$ Bacon-Shor code. The solid line on the upper boundary is the $p_T=p$ line.

Figure 5

Circuit for Steane's error correction on a non-CSS code. $\left|\overline{\psi }\right.〉$ is an arbitrary encoded state, and $\left|\overline{a}\right.〉$ is the $2n$-qubit ancilla state from Eq. (A3). The notation $\overline{n}$ and $\underline{n}$ means that the $n$ CZ gates are transversally coupled to the top $n$ qubits in the ancilla and that the $n$ cnot gates are transversally coupled to the bottom five qubits in the ancilla. Measurement is done transversally, from which the syndrome can be classically computed.

Figure 6

Preparing the error-correction ancilla state for the 5-qubit code for use in Fig. 5. Input states are all prepared in $\left|0\right.〉$.

Figure 7

Verification circuit for the ancilla state prepared by the circuit in Fig. 6. $\left|{\overline{a}}_n\right.〉$ is a noisy ancilla state that needs to be verified, and $\left|{\overline{a}}_p\right.〉$ is a purified one.

Figure 8

Circuit identity used for implementing the $S$ gate. Here $\left|S\right.〉=S\left|+\right.〉=(\left|0\right.〉+i\left|1\right.〉)/\sqrt{2}$.

Figure 9

Circuit volume for two different implementations of the Toffoli gate. Dashed: gate synthesis using a $T$ gate. Solid: Toffoli state scheme.