Analysis of physical requirements for simple three-qubit and nine-qubit quantum error correction on quantum-dot and superconductor qubits

The implementation of a scalable quantum computer requires quantum error correction (QEC). An important step toward this goal is to demonstrate the effectiveness of QEC where the fidelity of an encoded qubit is higher than that of the physical qubits. Therefore, it is important to know the conditions under which QEC code is effective. In this study, we analyze the simple three-qubit and nine-qubit QEC codes for quantum-dot and superconductor qubit implementations. First, we carefully analyze QEC codes and find the specific range of memory time to show the effectiveness of QEC and the best QEC cycle time. Second, we run a detailed error simulation of the chosen error-correction codes in the amplitude damping channel and confirm that the simulation data agreed well with the theoretically predicted accuracy and minimum QEC cycle time. We also realize that since the swap gate worked rapidly on the quantum-dot qubit, it did not affect the performance in terms of the spatial layout.

Figure 1

Memory and QEC time for the three-qubit QEC. This circuit was experimentally implemented in [5] and [6]. A QEC cycle consists of encoding, memory, decoding, and correction steps. Ideally the QEC can correct a single X error in the data qubit during the memory time. $T_{\mathrm{mem}}$, $T_{\mathrm{QEC}}$, and $T_{\mathrm{QEC}\mathrm{Cycle}}$ are the times for the memory, QEC, and QEC cycle, respectively. Note that $T_{\mathrm{QEC}\mathrm{Cycle}}=T_{\mathrm{mem}}+T_{\mathrm{QEC}}$. To periodically operate this QEC circuit, each ancilla qubit should be reset at the end of the correction process, which is omitted here.

Figure 2

Mapping of the nine-qubit QEC on 1D and 2D architectures. Due to the locality condition and the limit on the degree of interaction, multiple swap gates are augmented in the 1D architecture. The layout of the 1D structure was chosen such that it used few swap gates. After the last Toffoli gate, additional qubits (1–4, 6–9) should be reset and renamed like the beginning of the circuit.

Figure 3

cnot gate by multiple pulses. Each qubit technology supports arbitrary single-qubit gates. For the two-qubit gate, quantum-dot [19] and superconductor [20] qubits support $\mathrm{SWAP}\left(\theta \right)$ and $i\mathrm{SWAP}\left(\theta \right)$ interactions, respectively.

Figure 4

Toffoli gate by multiple pulses [1].

Figure 5

cnot gate by a single-shot pulse. Each plot shows the pulse waveform for the $x_1$, $x_2$, $y_1$, $y_2$, $z_1$, $z_2$, and $x_1{x}_2+y_1{y}_2+z_1{z}_2$ Hamiltonians, respectively. The horizontal line represents the time of the pulse sequence during unit time. The red (thin) curves show the final pulse shapes; the blue (thick) curves, the intermediate pulse shapes during pulse generation.

Figure 6

Gain of the three-qubit QEC with the memory time and physical error rate. The range in green representsthe memory time and physical error rate, showing positive gain ($F_e-F_p$) of the QEC. Dotted lines represent the theoretically calculated minimum memory time and accuracy threshold value listed in Table 4.

Figure 7

Converted circuit of the three-qubit QEC for the IBM test with an intended error and idle gates. The second qubit here was the third input to the IBM system.