Low-distance surface codes under realistic quantum noise

Experimental implementation of the surface code will be a significant milestone for quantum computing. We develop a circuit and a decoder targeted for near-term implementation of a distance-3 surface code. We simulate the code under amplitude and phase damping and compare the threshold to a Pauli-twirl approximation. We find that the approximation yields a pessimistic threshold estimate. From numerical Monte Carlo simulations, we identify the gate and measurement speeds required to achieve reliable error correction. For superconductor devices, a qubit encoded in a 17-qubit surface code demonstrates a lower error rate than an unencoded qubit assuming gate times of 5–40 ns and $T_1$ times of at least 1–2 $\mu \mathrm{s}$. If $T_1\ge 10$ ns, the difference is significant and can be experimentally measured, allowing near-term implementation and verification of a small surface code. For ion trap devices, gates times of 1 $\mu \mathrm{s}$ and $T_1\ge 40$ ms admit measurable differences in error rate.

Figure 1

Distance-3 surface code layouts with (a) 25, (b) 17, and (c) 13 qubits. White circles represent data qubits; black circles, syndrome qubits. Dark square and triangular patches represent $X$ stabilizers; light patches represent $Z$ stabilizers. The layered patches on surface-13 indicate use of the syndrome qubit first to measure a four-qubit stabilizer and then to measure a two-qubit stabilizer.

Figure 2

Standard quantum circuits to measure stabilizers (a) $X_a{X}_b{X}_c{X}_d$ and (b) $Z_a{Z}_b{Z}_c{Z}_d$.

Figure 3

Quantum circuits for measuring $X_0{X}_1{X}_3{X}_4$ and $Z_0{Z}_3$ in (a) surface-17 and (b) surface-13.

Figure 4

(a) Stabilizer measurement circuit showing the propagation of a $Z$ error to two $Z$ errors. (b) Reordered stabilizer measurement circuit.

Figure 5

Lookup table decoding rules. Each circle represents a syndrome measurement. Filled (red) circles indicate “flips.” Five types of flips are shown: (1) measurement error, (2, 3) paired flips indicating a single-qubit error on the data qubit, (4) a single flip indicating one data-qubit error, and (5) an undetermined flip. These numbers correspond to the rules in Sec. 3.

Figure 6

Circuit representation of amplitude damping [21].

Figure 7

Insertion of identity gates during simulation of the circuit in Fig. 3. Four identity gates are used, based on the other location type in the given time step: preparation (P), single-qubit gate (H), two-qubit gate (C), and measurement (M).

Figure 8

Illustration of the syndrome volume. Each window consists of three rounds of the surface code. Corrections are applied to the state after the final round in the window. The state is then checked for a logical error. An example window consists of the top three blue layers, where one layer overlaps with the previous window.

Figure 9

Location error rate $p$ versus logical error rate $P_{1,X}$ for a logical $|1_L\rangle$ state encoded in (a) surface-13, (b) surface-17, and (c) surface-25 under symmetric depolarizing noise.

Figure 10

Surface-17 logical $X$ error rate $P_{1,X}$ (red; qubit encoded in $|1_L\rangle$) and logical $Z$ error rate $P_{1,Z}$ (green; qubit encoded $|{+}_L\rangle$) under depolarizing noise.

Figure 11

Comparison of the logical error rate of a qubit encoded in surface-17 under amplitude and phase damping (green) and the Pauli-twirl approximation (red) for the ${\mathrm{SC}}_H$ setting. (a) Logical $Z$ error rate $P_{3,Z}$ (in the logical $|{+}_L\rangle$ state); (b) logical $X$ error rate $P_{3,X}$ (in the logical $|1_L\rangle$ state).

Figure 12

Left: 3D plots of $T_1$ time ($\mu \mathrm{s}$) vs memory duration (ns) vs $P_{3,X}$ for the ${\mathrm{SC}}_H$ setting under (a) the Pauli-twirl approximation and (b) amplitude and phase damping. The blue surface represents the amplitude damping probability at a given $T_1$ and memory duration (unencoded qubit). The yellow surface is the simulated logical error rate given $T_1$ for a qubit encoded in the $|1_L\rangle$ state in surface-17. The orange surface indicates the upper error bar on $P_{3,X}$. Right: 2D plots from the $+z$ axis. The blue and red regions indicate a range of $T_1$ times ($x$ axis) for which encoding a qubit in the $|1_L\rangle$ state in surface-17 reduces or increases, respectively, the logical error rate compared to an unencoded $|1\rangle$ qubit in memory for a range of durations ($y$ axis).

Figure 13

Plots of $T_1$ time ($\mu \mathrm{s}$) versus memory duration ($\mu \mathrm{s}$) for six architecture settings under amplitude and phase damping. The blue and red regions indicate a range of $T_1$ times ($x$ axis) for which encoding a qubit in $|1_L\rangle$ in surface-17 reduces or increases, respectively, the logical error rate compared to an unencoded $|1\rangle$ qubit in memory for a range of durations ($y$ axis). (c) ${\mathrm{SC}}_D$; (d) ${\mathrm{SC}}_H$.

Figure 14

Plots of $T_1$ time ($\mu \mathrm{s}$) versus the logical $X$ error rate $P_{3,X}$ for six architecture settings for a qubit encoded in $|1_L\rangle$ in surface-17 subject to amplitude and phase damping [(red) points] and an unencoded $|1\rangle$ qubit subject to amplitude damping [dashed (blue) line] for the duration of three rounds of the surface code.

Figure 15

Plots of four superconductor architecture settings under amplitude and phase damping for $T_1$ times up to $50\mu \mathrm{s}$. Left: Plots of $T_1$ time ($\mu \mathrm{s}$) versus memory duration ($\mu \mathrm{s}$) versus logical failure rate. Middle: Plots of $T_1$ time ($\mu \mathrm{s}$) versus memory duration ($\mu \mathrm{s}$). Right: Plots of $T_1$ time ($\mu \mathrm{s}$) versus logical failure rate. The blue and red regions indicate a range of $T_1$ times ($x$ axis) for which encoding a qubit in $|1_L\rangle$ in surface-17 reduces or increases, respectively, the logical error rate compared to an unencoded $|1\rangle$ qubit in memory for a range of durations ($y$ axis).