Fault-tolerant quantum computation with asymmetric Bacon-Shor codes

We develop a scheme for fault-tolerant quantum computation based on asymmetric Bacon-Shor codes, which works effectively against highly biased noise dominated by dephasing. We find the optimal Bacon-Shor block size as a function of the noise strength and the noise bias, and estimate the logical error rate and overhead cost achieved by this optimal code. Our fault-tolerant gadgets, based on gate teleportation, are well suited for hardware platforms with geometrically local gates in two dimensions.

Figure 1

Bacon-Shor qubits arranged in an $n\times m$ lattice.

Figure 2

$X$-type stabilizer operator (top) and $Z$-type stabilizer operator (bottom)

Figure 3

Gadget for a single row of the nondestructive ${\mathcal{M}}_Z^L$ measurement, where the cat state ancilla length $p$ is equal to the row length $m$.

Figure 4

One-bit teleportation circuit.

Figure 5

Four versions of the cnot gadget.

Figure 6

Teleported cnot gate.

Figure 7

Arrangement of Bacon-Shor qubits for geometrically local computation for $3\times 5$ code block. Large blue circles indicate data qubits, small green circles ancilla qubits. Solid lines indicate locations between which cz gates may be performed. Dotted lines separate qubits into code blocks. The ribbon may be extended arbitrarily far to the right and left with additional code blocks.

Figure 8

Optimal cnot logical error rate versus physical error rate for various values of the bias. Labels represent the $n\times m$ dimensions of the Bacon-Shor code block. For blocks with a single row, one can use the code studied in Ref. [8] which is a special case of the asymmetric Bacon-Shor code.

Figure 9

Optimal cnot logical error rate vs required number of physical gates for $n\times m$ asymmetric Bacon-Shor codes, for a physical error rate $\varepsilon ={10}^{-4}$ at various values of the bias, plotted alongside results for codes studied in Ref. [7] with no bias.

Figure 10

Optimal cnot logical error rate vs physical error rate for various values of the bias, where two-qubit physical gates are assumed to be geometrically local.

Figure 11

Optimal cnot logical error rate vs required number of physical gates for geometrically local asymmetric Bacon-Shor codes at various values of the bias, for a physical error rate $\varepsilon ={10}^{-4}$

Figure 12

Bacon-Shor block size vs optimal (in number of gates) cnot logical error rate for geometrically local asymmetric Bacon-Shor codes at various values of the bias, for a physical error rate $\varepsilon ={10}^{-4}$.

Figure 13

Optimal cnot logical error rate vs required number of gates for geometrically local asymmetric Bacon-Shor codes, assuming a physical error rate $\varepsilon ={10}^{-4}$, bias ${10}^4$, and various rates of the measurement error rate ${\varepsilon }_{\mathcal{M}}$.

Figure 14

Injection error probability for the optimal geometrically local Bacon-Shor codes found in Fig. 10, with the probability of an error on the unprotected state $|\psi \rangle$, ${\varepsilon }_{\psi }$, set to be equal to the dephasing error probability $\varepsilon$.

Figure 15

Output error probability after $n$ levels of $|T\rangle$ distillation, starting from ${\varepsilon }_{\text{in}}=0.15$, for various values of ${\varepsilon }_{\text{css}}$. The $|+i\rangle$ ancillas are assumed to be maximally distilled, so that ${\varepsilon }_{|+i\rangle }=4{\varepsilon }_{\text{css}}$. Eventually the output probability levels off to around $8{\varepsilon }_{\text{css}}$.

Figure 16

Output error probability after $n$ levels of $|T\rangle$ distillation, with the values of ${\varepsilon }_{\text{in}}$ and ${\varepsilon }_{\text{css}}$ taken from the optimal values of Fig. 14, for $\varepsilon ={10}^{-4}$ and various biases. Only two rounds of distillation are required in each case to reach the floor.