Applications of universal parity quantum computation

We demonstrate the applicability of a universal gate set in the parity encoding, which is a dual to the standard gate model, by exploring several quantum gate algorithms such as the quantum Fourier transform and quantum addition. Embedding these algorithms in the parity encoding reduces the circuit depth compared to conventional gate-based implementations while keeping the multiqubit gate counts comparable. We further propose simple implementations of multiqubit gates in tailored encodings and an efficient strategy to prepare graph states.

Figure 1

Realization of a single-qubit unitary in universal parity quantum computation by exploiting Eq. (7). cnot gates commute with $R_z$ gates acting on their control qubit. The $R_z$ gates on the data qubit can thus be moved through the cnot sequence and recombined to the unitary $U$ together with the $R_x$ rotation. The unitary $U$ acts locally on a physical qubit, while $\tilde{U}$ denotes a logical operation. The blue line represents the logical line corresponding to the qubit targeted by the operation.

Figure 2

Implementation of a cnot gate in the LHZ architecture. The gate count depends on the number of logical qubits $n$ and the distance $|c-t|$ between control ($c$) and target ($t$) qubits. cnot gates marked with a red cross cancel; the blue line represents the logical line corresponding to the target qubit. The outer $R_z$ rotations of the Hadamard gates are not shown; the $R_z$ gates on qubit $\left(t\right)$ have been merged.

Figure 3

Circuit for performing the QFT in the LHZ scheme. cnot gates are required to perform the logical Hadamard gates, while single-qubit $R_z$ rotations implement logical cphase gates. Gates which do not contribute to the circuit depth are faded out. For all but the first and the last line, increasing the system size would only add gates which do not contribute to the circuit depth. The diagram on the bottom visualizes the time steps occupied by each gate block of the QFT algorithm. In the layout on the left, lines depict logical lines and the gray squares and triangles represent parity constraints.

Figure 4

Implementation proposal for the quantum addition of two registers R1 (labeled with numbers) and R2 (labeled with letters) in the LHZ scheme. The embedding consists of three standard LHZ schemes, two encoding the interactions within register R1 and R2, respectively, and one encoding the interregister interactions. The solid lines represent logical lines for register R1 and the dashed lines the logical lines for qubits in register R2. The qubits encoding interactions within register R2 (white) can be left out if no operations are necessary in register R2.

Figure 5

Gate decomposition of a multicontrolled phase gate into Toffoli and ${\mathrm{CP}}_{\varphi }$ gates using ancilla qubits $A\text{−}C$, following Ref. [31].

Figure 6

Implementation layout for the $n$-controlled phase gate. Ancilla qubits are labeled with capital letters, parity qubits are shown in light gray, and data qubits are dark gray. Dotted lines indicate connectivity requirements between the physical qubits during computation. The parity encoding is reduced to the minimal required set of physical qubits such that only the ancilla qubits require (short) logical lines, shown by the colored lines.