Nonvolatile Memory with Multilevel Switching: A Basic Model

There is a current upsurge in research on nonvolatile two-terminal resistance random access memory (RRAM) for next generation electronic applications. The RRAM is composed of a simple sandwich of a semiconductor with two metal electrodes. We introduce here an initial model for RRAM with the assumption that the semiconducting part has a nonpercolating domain structure. We solve the model using numerical simulations and the basic carrier transfer mechanism is unveiled in detail. Our model captures three key features observed in experiments: multilevel switchability of the resistance, its memory retention, and hysteretic behavior in the current-voltage curve.

Figure 1

Schematic view of the model with top and bottom electrodes, insulating medium, smaller top and bottom domains, and large middle domains. In this work we set ${\Gamma }_{\mathrm{ET}}={\Gamma }_{\mathrm{EB}}=0.4\times {10}^{-16}$ and ${\Gamma }_{\mathrm{TM}}={\Gamma }_{\mathrm{BM}}=0.3\times {10}^{-11}$, the number of top and bottom domains to 40, and the number of states that they hold to ${10}^6$; the sole middle domain holds ${10}^8$ states.

Figure 2

(a) Top panel: Electrode current as a function of simulation time. The pulses have a duration of 10 uot. Positive pulses erase and negative pulses write. Middle panel: Idem as the top panel in an enlarged $y$-axis scale. Bottom panel: Resistance ($\propto 1/I$) as a function of simulation time. (b) Idem as (a) but for the multilevel switching protocol.

Figure 3

Top panel: Domain occupation as a function of simulation time. Top domains are in black and bottom domains are in gray. The middle domain occupation remains close to 0.5 (light gray). Note that the occupation of top and bottom saturates after the erase pulse, but not after the write one. Bottom panel: Idem to the top panel in an enlarged $x$-axis scale that highlights the rapid decharging and charging of the top and bottom domains during the pulse application.

Figure 4

$I\mathrm{\text{−}}V$ characteristic showing an hysteresis cycle. The voltage protocol corresponds to a positive ramp from $V=-4.5$ to $V=4.5$ during a time interval of 1500 uot (paths 1 and 2) and ramp back to $V=-4.5$ (paths 3 and 4).