Nonlinear Response of a Clean One-Dimensional Wire

We study nonlinear transport in a clean one-dimensional wire fabricated by cleaved edge overgrowth in molecular beam epitaxy. At low electron densities, and with a large applied bias, we observe a feature in the differential conductance similar to the so-called “0.7 structure,” found in quantum point contact devices. Using a simple model we suggest a link between this phenomenon, charge neutrality, and unidirectional dynamics in the wire.

Figure 1

Differential conductance vs gate voltage at different biases. (a) Differential conductance of a $2\mu \mathrm{m}$ long CEO wire at a bath temperature of 18 mK. An ac excitation of $18\mu \mathrm{V}$ was used in conjunction with a dc bias of 0, 1, 2, and 3 mV (solid lines). The conductance anomaly at low densities is more pronounced at a larger source-drain bias. Inset: Geometry of a CEO wire: A two-dimensional electron gas (2DEG) is formed in a 25 nm GaAs quantum well by modulation doping. The resultant 2DEG has a carrier density $n_s\approx 2.5\times {10}^{11}{\mathrm{c}\mathrm{m}}^{-2}$, and mobility $\mu \approx 4\times {10}^6{\mathrm{c}\mathrm{m}}^2/\mathrm{V}\mathrm{s}$. A second modulation doping sequence is then grown onto a freshly cleaved [011] facet to create the 1D wire along the cleaved edge. A tungsten gate evaporated onto the top surface is utilized to deplete the 2DEG and separate out the wire in front of it. The resultant two separate 2DEG sheets are used as source and drain reservoirs. (b) The numerical derivative of the differential conductance at a 3 mV bias [(a), black trace], with respect to the gate voltage. This quantity highlights the transitions between different conductance values, as shown. Inset: the conductance plateau is bound by the second subband at high densities and by depletion of left movers at low densities—see text.

Figure 2

Transconductance vs gate voltage and dc bias: The numerical derivative of the differential conductance with respect to gate voltage [see Fig. 1b] as a function of gate voltage and dc bias, in a color plot format. Data were taken with an ac excitation of $18\mu \mathrm{V}$ at a bath temperature of 18 mK. The red lines separate regions of different conductance values, as indicated. The data are largely symmetric with respect to the applied bias. The slight asymmetry results from unintentional device asymmetry that varied from device to device within the 3 wires measured. Superimposed on the data are the curves $u_{\Delta }(V_g)$, solid white line, and $u_0(V_g)$, solid black line (see text). The onset of the 0.7 anomaly corresponds to the $u_0(V_g)$ curve, which marks the depletion of left (right) movers at a positive (negative) bias.

Figure 3

Transconductance of the upper wire modes: (a) The numerical derivative of the differential conductance with respect to gate voltage, as a function of gate voltage and dc bias in a color plot format. Data were taken with an ac excitation of $18\mu \mathrm{V}$ at a bath temperature of 18 mK. The gate voltage range shown corresponds to the second through sixth wire modes. Solid lines: $u_{\Delta }(V_g)$ and $u_0(V_g)$ curves for each one of the wire modes (see text). (b) Left panel, blue squares: The capacitance between the gate and the $i$th wire mode, as calculated in a simple model (see text), plotted against the mode index. These capacitance values lead to the excellent agreement with the data in (a) as well as in Fig. 2. Right panel, green circles: the interchannel gaps ${\Delta }_{i\to i+1}$, as deduced from the data. The confinement energy of the first mode is $\sim 15\mathrm{m}\mathrm{e}\mathrm{V}$.