Probing the Debye Layer: Capacitance and Potential of Zero Charge Measured Using a Debye-Layer Transistor

We present a unique method for probing the properties of the electrolytic Debye layer, incorporating it as the active element in a novel radio frequency (rf) field-effect transistor. The capacitance of the Debye layer depends nonlinearly on the voltage applied across it, and we exploit this dependence to directly modulate the rf conductance between two nanofabricated interdigitated electrodes. We make quantitative measurements of the Debye-layer capacitance, allowing us to determine the potential of zero charge, a quantity of importance for electrochemistry and impedance-based biosensing.

Figure 1

(a) Scanning electron microscope image of portion of ten gold IDE fingers, $200\mathrm{nm}\times 40\mathrm{nm}$, separated by 200 nm and overlapping by $20\mu \mathrm{m}$ in length, electron-beam lithographed on glass. (b) Gate voltage $V_g$ is applied across the gate impedance $Z_g$: the electrolyte resistance $R_g$ in series with the EDL capacitance $C_{\mathrm{DL}}$. The rf impedance between IDEs is $Z_f$, boxed: the electrolyte response ($R_f$ in parallel with $C_f$), in series with the two $V_g$-dependent double-layer capacitances $C_{\mathrm{DL}}$. (c) The rf source voltage of amplitude $V_{\mathrm{in}}$ is reflected from an rf impedance-matching circuit $Z_m$, which consists of an inductance $L$, a variable capacitor (varactor diode) $C_V$, and the IDE device. A directional coupler (DC) diverts the reflected rf signal, of amplitude $V_{\mathrm{out}}$. (d) The rms voltage $V_{\mathrm{out}}$ (solid line) is plotted vs time as $V_g$ (dashed line) is switched at 1 Hz between off ($V_g=-400\mathrm{mV}$) and on ($V_g=-100\mathrm{mV}$) values.

Figure 2

Output voltage modulated by gate voltage. The rms amplitude $V_{\mathrm{out}}-{\overline{V}}_{\mathrm{out}}$ vs $V_{\mathrm{in}}-{\overline{V}}_{\mathrm{in}}$, for several values of the gate voltage $V_g$. Each trace comprises five amplitude cycles of $V_{\mathrm{in}}$, modulated at 1 kHz. We fit each trace to a straight line whose slope corresponds to the reflectance $|\Gamma (V_g)|$. The inset shows $|\Gamma (V_g)|/|{\Gamma }_{\mathrm{OFF}}|$ vs $V_g$. The shape of the curve is determined by the nonlinear voltage dependence of the EDL capacitance $C_{\mathrm{DL}}$ on $V_g$.

Figure 3

Normalized amplitude of first harmonic in the output $V_1(f)$ vs $f_g$ for three different devices. Each exhibits a roll-off in amplitude at the corresponding $f_{RC}$ of the gate impedance $Z_g$. A least squares fit to curve A between 15 and 80 Hz (dashed line) yields a dependence $1/f_g^{0.8}$. The inset shows $|Z_g|$ vs $f_g$ corresponding to curve A. For frequencies below $f_{RC}=1/(2\pi RC)\sim 10\mathrm{Hz}$ (vertical dashed line), the EDL capacitance $C_{\mathrm{DL}}$ dominates $Z_g$, while above this frequency $R_g$ dominates. The impedance of $R=300\mathrm{k}\Omega$ in series with an ideal capacitance of $C=45\mathrm{nF}$ is shown by the curved dashed line. As $R_g$ (curve B) or both $R_g$ and $C_{\mathrm{DL}}$ (curve C) decrease, the roll-off frequency $f_{RC}$ increases. Curve C shows gating of the device output ($\nu =100\mathrm{MHz}$) at $f_g=5\mathrm{MHz}$.

Figure 4

Modulation of $V_{\mathrm{out}}$ (solid line) vs time with $V_g$ (dashed line) for comparison. In (a), $f_g=0.2\mathrm{Hz}<f_{RC}$, and $V_{\mathrm{out}}$ oscillates in phase with $V_g$. In (b), $f_g=5\mathrm{Hz}>f_{RC}$, and $V_{\mathrm{out}}$ has phase $-\pi /2$ with respect to $V_g$. Here the device was operating in $1\mathrm{m}M$ NaCl, with $f_{RC}\approx 1\mathrm{Hz}$.

Figure 5

(a) $C_1$ (solid line), $C_2$ (dashed line), and $C_1^{*}$ (dotted-dashed line) are plotted vs ${\overline{V}}_g$. (b) The phases ${\varphi }_1$ of $V_1$ (solid line) and ${\varphi }_2$ of $V_2$ (dashed line) relative to $V_g$ are plotted vs $V_g$. Phase changes of $\sim \pi$ are clear in both ${\varphi }_1$ and ${\varphi }_2$, indicating the zero crossings of $C_1$ and $C_2$, respectively. (c) Integrating $C_1$ in (a) yields $\Delta C_{\mathrm{DL}}$, which exhibits a peak at ${\overline{V}}_g=-170\mathrm{mV}$ (arrow). (d) Plot of $\Delta C_{\mathrm{DL}}$ vs ${\overline{V}}_g$ as the IDEs are biased directly with voltage $V_e$. For each value of $V_e$, $C_1$ is approximately linear in ${\overline{V}}_g$ and yields the quadratic $C_{\mathrm{DL}}$ minimum shown when integrated. $C_{\mathrm{DL}}$ depends only on the potential difference $V_g-V_e$ across the EDL.