Enhancement-mode double-top-gated metal-oxide-semiconductor nanostructures with tunable lateral geometry

We present measurements of silicon (Si) metal-oxide-semiconductor (MOS) nanostructures that are fabricated using a process that facilitates essentially arbitrary gate geometries. Stable Coulomb-blockade behavior showing single-period conductance oscillations that are consistent with a lithographically defined quantum dot is exhibited in several MOS quantum dots with an open-lateral quantum-dot geometry. Decreases in mobility and increases in charge defect densities (i.e., interface traps and fixed-oxide charge) are measured for critical process steps, and we correlate low disorder behavior with a quantitative defect density. This work provides quantitative guidance that has not been previously established about defect densities and their role in gated Si quantum dots. These devices make use of a double-layer gate stack in which many regions, including the critical gate oxide, were fabricated in a fully qualified complementary metal-oxide semiconductor facility.

Figure 1

(Color) (a) Optical image of an etch-defined device before both secondary dielectric and global top-gate deposition. The following features are identified: (I) $n+\text{implanted}$ ohmic contacts extending into a window etched into the deposited field oxide, (II) exposed gate oxide within the etched oxide window, and (III) etched polysilicon gates patterned with electron-beam lithography. (b) Cross-sectional schematic after processing in the CMOS facility. (c) Cross-sectional schematic of the completed layer structure corresponding to the line cut indicated by the dashed horizontal line in (a).

Figure 2

(a) Scanning electron microscope (SEM) image of Si nanostructure without ${\text{Al}}_2{\text{O}}_3$ or Al top gate; (b) tilted SEM image of completed device with both ${\text{Al}}_2{\text{O}}_3$ and Al top gate; and (c) SEM cross section after focused ion-beam cut of a completed device through gate H at the position shown by the solid horizontal line in (a).

Figure 3

(Color) (a) Transport through point contacts in sample A; conduction is plotted as a depletion gate voltage is applied to both gates B and H (solid trace) and gates F and H (dotted trace) with a top-gate voltage of $V_{\text{TG}}=25\text{V}$ and an applied ac source-drain voltage of $100\mu \text{V}$. Inset: transport through the gated quantum dot shown in Fig. 2a as a function of $V_{\text{D}}$ showing small amplitude Coulomb-blockade oscillations $V_{\text{T}}=25\text{V}$, $V_{\text{B}}=V_{\text{F}}=0$, $V_{\text{H}}=-100\text{mV}$, and $V_{\text{C}}=V_{\text{E}}=-500\text{mV}$. (b) Transport through a point contact in sample B, which was fabricated without a forming-gas anneal; conduction is plotted as a depletion gate voltage is applied to both gates A and B with a top gate voltage of $V_{\text{TG}}=8\text{V}$ and an applied ac source-drain voltage of $100\mu \text{V}$. Instead of a monotonic decrease in conduction, disorder within the channel produces resonances through pinch-off characteristic of the formation of quantum dots within the constriction.

Figure 4

(Color) (a) Conductance as a function of the voltage on gate E through the quantum dot, formed by gates D, E, F, and H shown in Fig. 2a. The voltages on the remaining gates are $V_{\text{Top}\text{Gate}}=+5\text{V}$, $V_{\text{D}}=-800\text{mV}$, $V_{\text{F}}=-2.3\text{V}$, and $V_{\text{H}}=-900\text{mV}$. (b) Conductance as a function of source-drain voltage and the voltage on gate E. Voltages on the remaining gates are $V_{\text{Top}\text{Gate}}=+5\text{V}$, $V_{\text{D}}=-800\text{mV}$, $V_{\text{F}}=-2.1\text{V}$, and $V_{\text{H}}=-900\text{mV}$.

Figure 5

(Color) (a) Results of an electrostatic simulation of a quantum-dot structure similar to that shown in Fig. 2a. Blue regions in the figure represent depletion gates, magenta regions correspond to areas where the metallic top gate comes within a vertical distance of 95 nm of the ${\text{Si-SiO}}_2$ interface, as noted. The locations of the 2DEG leads and the quantum dot are shown using a black contour marking the conduction edge. (b) Gate labels and representative meshing for 3D capacitance modeling. The area indicated by the black box corresponds to the portion of the device modeled in (a). (c), (d), and (e) 3D rendering of the doped polysilicon depletion gate layer, the dielectric layer, and the metallic top-gate layer, respectively, used in the 3D capacitance modeling. The results of which are shown in Table .

Figure 6

(Color) A simulation of bare potential with random distribution of charges located within the oxide, 2 nm from the ${\text{Si-SiO}}_2$ interface with a charge density of (a) $1\times {10}^{10}\text{charges}/{\text{cm}}^2$, (b) $1\times {10}^{11}\text{charges}/{\text{cm}}^2$, (c) $1\times {10}^{12}\text{charges}/{\text{cm}}^2$, and (d) $+5\times {10}^{10}\text{charges}/{\text{cm}}^2$ combined with $-5\times {10}^{10}\text{charges}/{\text{cm}}^2$ for a net zero charge at the interface. Contour spacing in each plot is 6 mV. Boxes represent a guide for an area of approximately $50\text{nm}\times 50\text{nm}$ representative of dimensions approximately the size of the point-contact dimension.