Quantized electron transfer through random multiple tunnel junctions in phosphorus-doped silicon nanowires

We have demonstrated numerically and experimentally that quantized electron transfer can be achieved in single-gated random multiple tunnel junctions. Extensive Monte Carlo simulations based on Coulomb blockade orthodox theory show that nonhomogeneous distributions of capacitances energetically favor one-by-one electron shuttling between the electrodes during each cycle of a gate voltage. This numerical prediction is supported by our experimental results on Si nanowire field-effect transistors with the channel moderately doped with phosphorus. Ionized dopants within the device channel locally modulate the potential, creating a naturally random one-dimensional multiple-tunnel-junction array. Under ac-gate operation, small current plateaus or inflections aligned at $\pm nef$ appear in the $I_d\text{−}{V}_d$ characteristics, suggesting that quantized electron transfer is achievable in such naturally disordered systems.

Figure 1

(Color online) (a) Equivalent circuit of typically investigated 1D arrays. (b) Example of ac $I_d\text{−}{V}_d$ characteristics for uniform junction capacitances and resistances. Current plateaus can be observed at $nef$ levels. (c) Effect of gate capacitance dispersion on quantized electron transfer. Rate $r$ is defined as the number ratio of gate capacitance arrangements exhibiting quantized electron-transfer plateaus to all 16 investigated configurations.

Figure 2

(Color online) (a) Equivalent circuit of 1D arrays for investigating the effects of junction parameter randomness. (b) ac $I_d\text{−}{V}_d$ characteristics simulated for uniform junction capacitances and resistances. An $ef$ current plateau appears aligned around $V_d=0\mathrm{V}$. (c) Effect of junction capacitance dispersion on quantized electron transfer. Rate $r$ is defined as the number ratio of junction capacitance arrangements that exhibit the $ef$ current plateau to all 16 investigated configurations. [(d) and (e)] System free energy profiles calculated at $V_d=0\mathrm{V}$ for the system shown in (a) as a function of electron position during one gate voltage pulse, i.e., at $V_g^H=100\mathrm{mV}$ and at $V_g^L=0\mathrm{mV}$, respectively.

Figure 3

(Color online) [(a) and (b)] Equivalent circuits for 1D arrays with four and five quantum dots, respectively, and parameters chosen for analysis. [(c) and (d)] Mesh plots of average number of electrons transferred between the electrodes per cycle $(N_e∕\text{cycle})$ as a function of source-drain bias $V_d$ and source-side gate capacitance $C_{g1}$ for the cases of (a) and (b), respectively.

Figure 4

(Color online) Experimental dc $I_d\text{−}{V}_g$ characteristics for a reference undoped-channel FET (dotted curve) and for a FET having the same dimensions but the channel moderately doped with phosphorus (solid curve).

Figure 5

(Color online) [(a) and (b)] $I_d\text{−}{V}_d$ characteristics measured under dc operation (dashed curves) and ac operation (solid curves) for the doped-channel FET for offset gate voltages of $-0.39$ and $-0.6\mathrm{V}$, respectively. Small plateaus aligned around $\pm nef$ current levels can be noticed in both cases. (c) $I_d$ at $V_d=0\mathrm{V}$ under ac operation as a function of gate offset voltage $V_{g0}$.