Zero-bias anomaly and possible superconductivity in single-walled carbon nanotubes

We report measurements of field-effect transistors made of isolated single-walled carbon nanotubes contacted by superconducting electrodes. For large negative gate voltage, we find a dip in the low-bias differential resistance. Remarkably, this dip persists well above the superconducting transition temperature of the electrodes, indicating that it is not caused by superconducting proximity effect from the electrodes. This conclusion is supported by measurements on carbon nanotubes contacted by normal electrodes showing similar features. One possible explanation is superconductivity in the nanotubes, occurring when the gate voltage shifts the Fermi energy into van Hove singularities of the electronic density of states.

Figure 1

(Color online) (a) Schematic of CNFET No. 1. The nanotube is indicated by CNT and the dark region between the niobium and the nanotube represents a thin palladium layer. (b) Gate-voltage dependence of differential conductance at $4.2\mathrm{K}$ and zero bias. (c) Temperature dependence of differential resistance at zero bias, and $V_G=-47\mathrm{V}$.

Figure 2

(Color online) Differential resistance as a function of bias and temperature for CNFET No. 1. $V_G=-47\mathrm{V}$ for the dip on the left. $V_G=-48\mathrm{V}$ for peak on the right. The temperatures for the curves shown in (c) are 5.5, 8.5, 9.5, 15, 20, and $30\mathrm{K}$. The temperatures for the curves shown in (d) are 3, 4, 7, 9, 15, and $20\mathrm{K}$.

Figure 3

(Color online) (a) Schematic of CNFET No. 2. (b) Differential resistance as a function of temperature at gate voltage of $-35.7\mathrm{V}$ and zero bias. (c) Differential resistance as a function of bias for different temperature at $V_G=-35.7\mathrm{V}$.

Figure 4

(Color online) Differential resistance versus gate voltage for CNFET No. 2. (a) Temperature dependence of the gate sweep at zero bias. (b) Differential resistance versus bias and gate voltage at $T=4.2\mathrm{K}$ for CNFET No. 2, darker is more conducting.

Figure 5

(a) Gate sweep at zero bias for one cooldown of CNFET No. 2, where we could find an additional region of gate voltage showing the zero-bias anomaly, centered at $-23\mathrm{V}$ and marked as ZBA2. (b) Differential resistance vs bias at $V_G=-23\mathrm{V}$.

Figure 6

(Color online) Differential resistance versus temperature (a) and bias (b) for CNFET No. 3. (c) Differential resistance versus gate voltage around $-15.2\mathrm{V}$ for two temperatures.

Figure 7

(Color online) Differential resistance versus temperature for CNFET No. 2, at $V_G=-35.7\mathrm{V}$. The smooth curve is numerically simulated based on ballistic interference model. The ragged line is experimental data, taken from Fig. 4b.

Figure 8

(Color online) (a) Andreev reflection for an asymmetric $N∕\mathrm{NT}∕N$ device. (b) The temperature dependence of the Andreev reflection resistance dip. (c) Numerically reconstructed hypothetical superconducting energy gap $\Delta \left(T\right)$ inside NT.

Figure 9

(Color online) (a) Andreev reflection for an asymmetric $SN∕\mathrm{NT}∕NS$ device. (b) The temperature dependence of the Andreev reflection resistance dip. (c) Numerically reconstructed hypothetical nanotube gap $\Delta \left(T\right)$ with ${\Delta }_0=5.5\mathrm{meV}$.