Finite-element analysis of a silicon-based double quantum dot structure

We present finite-element solutions of the Laplace equation for the silicon-based trench-isolated double quantum dot and the capacitively-coupled single-electron transistor device architecture. This system is a candidate for charge and spin-based quantum computation in the solid state, as demonstrated by recent coherent-charge oscillation experiments. Our key findings demonstrate control of the electric potential and electric field in the vicinity of the double quantum dot by the electric potential applied to the in-plane gates. This constitutes a useful theoretical analysis of the silicon-based architecture for quantum information processing applications.

Figure 1

A schematic representation of the Si IDQD device used in the numerical simulations. Rectangular approximations are made to the device elements. (a) A view of the $x\text{−}y$ plane at the level of the dashed line in (b). (b) A view of the $x\text{−}z$ plane at the level of the dashed line in (a). The trenchlike structures are connected to the in-plane metal gates through a column of air. Each trench extends about $150\mathrm{nm}$ above the oxide base.

Figure 2

Two-dimensional slices taken from the full three-dimensional solution of the Laplace equation. (a) A slice from the $x\text{−}y$ plane at $z=420\mathrm{nm}$, through the center of the gates and IDQD. (b) A slice from the $x\text{−}z$ plane at $y=190\mathrm{nm}$, through the center of gate G2. The gate G4, is set to $-4.8\mathrm{V}$. The gates G1, G2, and G3 are set to $+1$, 2, and $-1\mathrm{V}$ respectively. The position of the IDQD is outlined.

Figure 3

Cross-sectional curves through the IDQD with $x=320\mathrm{nm}$ and $z=420\mathrm{nm}$ (the dots of each curve correspond to nodal points of the computational grid). The gate G4 is set to $-4.8\mathrm{V}$. (a) The electrostatic potential of the voltage on gate G2 is changed from $-5\text{to}+5\mathrm{V}$. (b) The voltage applied to gate G1 is varied from $0\text{to}-5\mathrm{V}$. The voltage applied to gate G3 is set to the negative of that applied to gate G1 (in order to maximize the electric field).