Origin of switching noise in $\mathrm{Ga}\mathrm{As}∕{\mathrm{Al}}_x{\mathrm{Ga}}_{1-x}\mathrm{As}$ lateral gated devices

We have studied switching (telegraph) noise at low temperature in $\mathrm{Ga}\mathrm{As}∕{\mathrm{Al}}_x{\mathrm{Ga}}_{1-x}\mathrm{As}$ heterostructures with lateral gates and introduced a model for its origin, which explains why noise can be suppressed by cooling samples with a positive bias on the gates. The noise was measured by monitoring the conductance fluctuations around $e^2∕h$ on the first step of a quantum point contact at around $1.2\mathrm{K}$. Cooling with a positive bias on the gates dramatically reduces this noise, while an asymmetric bias exacerbates it. Our model is that the noise originates from a leakage current of electrons that tunnel through the Schottky barrier under the gate into the conduction band and become trapped near the active region of the device. The key to reducing noise is to keep the barrier opaque under experimental conditions. Cooling with a positive bias on the gates reduces the density of ionized donors. This builds in an effective negative gate voltage so that a smaller negative bias is needed to reach the desired operating point. This suppresses tunneling from the gate and hence the noise. The reduction in the density of ionized donors also strengthens the barrier to tunneling at a given applied voltage. Further support for the model comes from our direct observation of the leakage current into a closed quantum dot, around ${10}^{-20}\mathrm{A}$ for this device. The current was detected by a neighboring quantum point contact, which showed monotonic steps in time associated with the tunneling of single electrons into the dot. If asymmetric gate voltages are applied, our model suggests that the noise will increase as a consequence of the more negative gate voltage applied to one of the gates to maintain the same device conductance. We observe exactly this behavior in our experiments.

Figure 1

Conductance $G$ of the quantum point contact measured in sample 1 as a function of gate voltage $V_{\mathrm{g}}$. $V_{\mathrm{g}}$ is defined as the average gate voltage applied to the gates, $V_{\mathrm{g}}=\frac{1}{2}(V_{\mathrm{g}1}+V_{\mathrm{g}2})$. The trace was taken with symmetric gate voltages so that the difference $\Delta V_{\mathrm{g}}=V_{\mathrm{g}1}-V_{\mathrm{g}2}=0$ after cooling the sample with zero bias voltage $(V_{\mathrm{gc}}=0)$ applied on the gates. Top inset: conductance as a function of time $t$ with $V_{\mathrm{g}}$ set to the value marked by the cross. Lower inset: SEM picture of the device showing the two gates used to define the QPC in the 2DEG.

Figure 2

Effect of bias cooling on sample 1. (a) QPC gate voltage characteristic for several bias voltages $V_{\mathrm{gc}}$ applied during cooldown. Inset: shift $\Delta V_{\mathrm{d}}$ of the depletion threshold measured for each cooling bias. The line is a guide to the eye showing a shift equal to the applied bias. (b) Time traces taken at maximum sensitivity for each bias. The traces are shifted vertically for clarity.

Figure 3

Mean frequency $f$ of the switching noise as a function of cooling bias $V_{\mathrm{gc}}$ for three different samples fabricated on the same wafer. The lowest curve was obtained on sample 1 and has $f=0$ for $V_{\mathrm{gc}}>0.26\mathrm{V}$. Inset: leakage current $I_{\mathrm{g}}$ as a function of $V_{\mathrm{g}}$ measured at room temperature for sample 2.

Figure 4

Effect of gate voltage asymmetry. Traces of $G$ as a function of time taken for different positive and negative value of the gate voltage difference $\Delta V_{\mathrm{g}}$ after cooling sample 1 with a positive bias $V_{\mathrm{gc}}=+0.26\mathrm{V}$ on both gates. Traces are offset for clarity. For each trace, the voltages (in V) applied on gates 1 and 2 used to set the QPC to maximum sensitivity are indicated in parentheses.

Figure 5

Profiles of conduction band under a large gate (a) for a sample cooled without gate bias, (b) during cooling with a gate bias of $V_{\mathrm{gc}}=+0.2\mathrm{V}$, and (c) after removing the bias applied in (b). The chemical potential of the gate ${\mu }_{\mathrm{m}}$ is pinned at an energy $e{V}_{\mathrm{b}}$ below the GaAs conductance band by the surface states, while the chemical potential of the semiconductor ${\mu }_{\mathrm{s}}$ is pinned by DX centers at an energy $E_{\mathrm{DD}}$ below the conduction band in the neutral region of the doped layer.

Figure 6

(a) Conduction band profile for a gate voltage of $V_{\mathrm{g}}=-0.4\mathrm{V}$ applied to a sample cooled without bias. Electrons are able to tunnel from the gate into the doped layer. (b) Conduction band profile for the same operating point after a bias cool of $V_{\mathrm{gc}}=+0.2\mathrm{V}$. Because of the built-in gate voltage, only $V_{\mathrm{g}}=-0.2\mathrm{V}$ is needed to achieve the same effective gate voltage of $-0.4\mathrm{V}$. Tunneling into the doped layer is no longer possible.

Figure 7

(a) Conductance $G$ of the QPC defined between gates D and S as a function of the voltage $V_{\mathrm{P}}$ applied to gate P. $V_{\mathrm{P}}$ is first swept from $+0.26\mathrm{V}\text{to}-0.45\mathrm{V}$ (top curve) and then back to $+0.26\mathrm{V}$ (bottom curve). Inset: SEM picture of the device showing the labels of the gates. The dot is $0.7\mu \mathrm{m}$ in diameter. (b) Evolution of the sensor conductance with time $t$ after ramping $V_{\mathrm{P}}$ quickly from $+0.26\mathrm{V}\text{to}0\mathrm{V}$. Inset: normalized step height $\Delta G$ plotted for the first 20 charging events.