Planar multipole ion trap

We report on the realization of a chip-based multipole ion trap manufactured using microelectromechanical systems technology, requiring minimal manual alignment of the electrodes. It provides ion confinement in an almost field-free volume between two planes of radiofrequency electrodes, deposited on glass substrates, which allows for optical access to the trap. An analytical model of the effective trapping potential is presented and compared with numerical calculations. Stable trapping of argon ions is achieved, and a lifetime of 16 s is measured. Electrostatic charging of the chip surfaces is studied and found to agree with a numerical estimate.

Figure 1

(Color online) Schematic view of the planar multipole ion trap with equidistant electrodes in two nearby planes. The electrodes are alternatingly connected to two opposing radio-frequency potentials to provide confinement between the planes. Their width amounts to $500\pm 5\mu \text{m}$ at a spacing of $\pi x_0=1000\pm 5\mu \text{m}$ and $z_0=5.0\pm 0.1\text{mm}$.

Figure 2

(Color online) The right panel shows the analytically calculated effective trapping potential along the $z$ direction (black line). The one-dimensional cut obtained from a two-dimensional numerical calculation of the effective potential (red line) cannot be distinguished from the analytical model. The result of the two-dimensional calculation is shown as a contour plot in the left panel for 16 stripes on each plane. One can clearly see the flat bottom and the steep walls of the effective potential. The nonadiabatic regions, where no stable trapping is possible, are colored in white.

Figure 3

(Color online) Photograph of one of the two ion trap chips mounted into its holder. The second chip (not shown) is mounted 5 mm above, facing the first chip. The metal bars surrounding the chip serve to shield the chip from electrostatic charging.

Figure 4

Number of ions extracted from the trap after different storage times. The data points are averaged over a series of individual measurements. Where the accuracy of the average is not indicated by error bars it is denoted by the symbol size. The solid line is showing an exponential fit with a lifetime of 16 s.

Figure 5

(Color online) The picture shows a cut through the chip. The high-resistive region (substrate), enclosed by two conducting parts (electrodes), can be charged by a current of free electrons. The circuit diagram shows how the charging current that hits the surface elements, $dA$, is discharged along surface in the $x$ direction, described by the differential resistances $dR$ and capacitances $dC$.

Figure 6

The picture shows a decrease in trapping efficiency after changing from two loading cycles per second to five loading cycles per second. The increase on the right side of the graph is the result of switching back again to two loading cycles per second.